1. Technical Field
Embodiments relate generally to signal transmission and more particularly, but not exclusively, to configuring circuit logic for implementing a signal modulation.
2. Background Art
Architectures for next generation processors are expected to rely on circuitry which provides an optical link interface between electrical domain high speed input/output (I/O) links of the processor and optical domain silicon photonic. Such interface circuitry will have to provide for data modulation/demodulation which accommodates optical domain links operating at over twice the speed of electrical domain links.
To date, processors have relied upon gasket chips which implement a 2:1 serializer-deserializer (SerDes) to perform data multiplexing and retiming for data rate conversion. However, among other limitations, gasket chips occupy large amounts of motherboard real estate, add timing latency (˜8-10 unit intervals), require around 2-3 W per-channel power consumption and pose motherboard routing complexities due to high speed differential routing. Accordingly, it is desirable to identify data rate conversion mechanisms which are more efficient than those of existing gasket chip hardware.